1. Field of Invention
This invention relates to IC fabrication, and more particularly to a process for fabricating crown capacitors of dynamic random access memory (DRAM), and to a capacitor structure for DRAM with crown capacitors.
2. Description of Related Art
A DRAM cell typically has a MOS transistor and a capacitor coupled thereto. Current capacitor types for DRAM include crown capacitor and trench capacitor. In advanced DRAM manufacturing processes, crown capacitors are more advantageous.
FIGS. 1A-1F illustrate, in a cross-sectional view, a conventional process for fabricating crown capacitors of DRAM.
Referring to FIG. 1A, a stacked structure of a target layer 102 formed with S/D contacts therein (not shown), a template layer 104 and a support layer 106 is provided. A patterned photoresist layer 108 is formed on the support layer 106, having therein hole patterns 109 for defining the holes serving as templates of the crown capacitors.
Referring to FIG. 1B, the support layer 106 and the template layer 104 are etched anisotropically using the photoresist layer 108 as a mask to form, in the template layer 104, holes 110 exposing the S/D contacts (not shown), and the photoresist layer 108 is removed. Due to inclined plasma etching in the etching process, bowing 112 occurs to the sidewall of each hole 110 at a depth within the range of about 1-6 times of the size of the hole 110 from the hole top, wherein the depth depends on the etching recipe.
Referring to FIG. 1C, a conformal conductive layer 114 is then formed over the resulting structure, and a sealing layer 116 is formed sealing the holes 110.
Referring to FIG. 1D, a portion of the sealing layer 116 and a portion of the conductive layer 114 on the support layer 106 are removed to expose the support layer 106, so that the conductive layer 114 is divided into lower electrodes 114a. 
Referring to FIG. 1E, a patterned photoresist layer 118 is formed covering a part of the remaining support layer 106, and the exposed part of the same is removed to expose the template layer 104, while the exposed part of the sealing layer 116 and the exposed upper portion of each lower electrode 114a are also removed.
Referring to FIG. 1F, the photoresist layer 108 is removed, and the remaining sealing layer 116 and the template layer 104 are removed with wet etching. As a result, the lower electrodes 104a is supported by the support layer 106 only.
After that, a dielectric layer and the upper electrodes of the crown capacitors are formed as usual, which is well known in the art and is not shown here.
The above process is suitable in fabricating DRAM of high integration degree. However, the lower electrodes 114a are easily damaged in the etching of the support layer 106 shown in FIG. 1E, and there is a loss “h” at the upper part of each lower electrode 114a decreasing the capacitance of the capacitor formed later. Besides, when the above etching process of the support layer 106 is controlled to prevent loss at the upper part of each lower electrode 114a, the exposed portion of the upper part of each lower electrode 114a is easily broken to form undesired particles.
Moreover, when the bowing 112 of the sidewalls of the holes 110 in the template layer 104 is too much, two neighboring holes 110 are connected with each other at their sidewall bowing portions so that the two neighboring lower electrodes 114a formed in them are shorted with each other. Hence, the distance between two neighboring holes 110 is difficult to decrease, so that the lateral area of each capacitor or the integration degree of DRAM is difficult to increase.